/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020 Google LLC.
 */
#ifndef __TPUV1_IOCTL_H__
#define __TPUV1_IOCTL_H__ 
#ifdef __KERNEL__
#include <linux/google/gasket.h>
#endif
#include <linux/ioctl.h>
#ifndef __KERNEL__
#include <stdint.h>
#endif
#define TPUV1_NUM_BARS 3
#define TPUV1_TN_BAR_INDEX 2
#define TPUV1_LBUS_BAR_INDEX 0
#define TPUV1_PAGE_SHIFT 12
#define TPUV1_PAGE_SIZE (1 << TPUV1_PAGE_SHIFT)
#define TPUV1_EXTENDED_SHIFT 63
#define TPUV1_ADDR_SHIFT 3
#define TPUV1_LEVEL_SHIFT (TPUV1_PAGE_SHIFT - TPUV1_ADDR_SHIFT)
#define TPUV1_LEVEL_SIZE (1 << TPUV1_LEVEL_SHIFT)
#define TPUV1_PAGE_TABLE_MAX 65536
#define TPUV1_SIMPLE_PAGE_MAX TPUV1_PAGE_TABLE_MAX
#define TPUV1_EXTENDED_PAGE_MAX (TPUV1_PAGE_TABLE_MAX << TPUV1_LEVEL_SHIFT)
#define TPUV1_RESET_RETRY 1200
#define TPUV1_RESET_DELAY 10
#define TPUV1_CHIP_INIT_DONE 2
#define TPUV1_RESET_ACCEPTED 0
#define TPUV1_LBUS_BAR_OFFSET 0x10000000
#define TPUV1_TN_BAR_OFFSET 0
#define TPUV1_NUM_MIRROR_REGISTERS 12
enum tpuv1_reset_types {
 TPUV1_CHIP_REINIT_RESET = 3
};
enum tpuv1_interrupt {
 TPUV1_INTERRUPT_TN0_HBM_WRITE_QUEUE = 0,
 TPUV1_INTERRUPT_TN0_NF_DESCRIPTOR_QUEUE = 1,
 TPUV1_INTERRUPT_TN0_CHIP_DEBUG_QUEUE = 2,
 TPUV1_INTERRUPT_TN0_TC_INFEED_QUEUE = 3,
 TPUV1_INTERRUPT_TN0_BC_INFEED_QUEUE = 4,
 TPUV1_INTERRUPT_TN0_TC_OUTFEED_QUEUE = 5,
 TPUV1_INTERRUPT_TN0_BC_OUTFEED_QUEUE = 6,
 TPUV1_INTERRUPT_TN0_BC_FSM_MICROCODE_QUEUE = 7,
 TPUV1_INTERRUPT_TN0_NF_OUTFEED_QUEUE = 8,
 TPUV1_INTERRUPT_TN0_TC_HOST_0 = 9,
 TPUV1_INTERRUPT_TN0_TC_HOST_1 = 10,
 TPUV1_INTERRUPT_TN0_TC_HOST_2 = 11,
 TPUV1_INTERRUPT_TN0_TC_HOST_3 = 12,
 TPUV1_INTERRUPT_TN0_TC_HALTED = 13,
 TPUV1_INTERRUPT_TN1_HBM_WRITE_QUEUE = 14,
 TPUV1_INTERRUPT_TN1_NF_DESCRIPTOR_QUEUE = 15,
 TPUV1_INTERRUPT_TN1_CHIP_DEBUG_QUEUE = 16,
 TPUV1_INTERRUPT_TN1_TC_INFEED_QUEUE = 17,
 TPUV1_INTERRUPT_TN1_BC_INFEED_QUEUE = 18,
 TPUV1_INTERRUPT_TN1_TC_OUTFEED_QUEUE = 19,
 TPUV1_INTERRUPT_TN1_BC_OUTFEED_QUEUE = 20,
 TPUV1_INTERRUPT_TN1_BC_FSM_MICROCODE_QUEUE = 21,
 TPUV1_INTERRUPT_TN1_NF_OUTFEED_QUEUE = 22,
 TPUV1_INTERRUPT_TN1_TC_HOST_0 = 23,
 TPUV1_INTERRUPT_TN1_TC_HOST_1 = 24,
 TPUV1_INTERRUPT_TN1_TC_HOST_2 = 25,
 TPUV1_INTERRUPT_TN1_TC_HOST_3 = 26,
 TPUV1_INTERRUPT_TN1_TC_HALTED = 27,
 TPUV1_INTERRUPT_ERROR = 28,
 TPUV1_INTERRUPT_LINK = 29,
 TPUV1_INTERRUPT_COUNT = 30,
 TPUV2_INTERRUPT_TN0_BC_HOST_0 = 30,
 TPUV2_INTERRUPT_TN0_BC_HOST_1 = 31,
 TPUV2_INTERRUPT_TN0_BC_HOST_2 = 32,
 TPUV2_INTERRUPT_TN0_BC_HOST_3 = 33,
 TPUV2_INTERRUPT_TN1_BC_HOST_0 = 34,
 TPUV2_INTERRUPT_TN1_BC_HOST_1 = 35,
 TPUV2_INTERRUPT_TN1_BC_HOST_2 = 36,
 TPUV2_INTERRUPT_TN1_BC_HOST_3 = 37,
 TPUV2_INTERRUPT_COUNT = 38
};
struct tpuv1_tc_csr_access {
 int tensor_node;
 int enable;
};
#define TPUV1_IOCTL_BASE 0x7F
#define TPUV1_IOCTL_SET_DEBUG_TC_CSR_ACCESS \
 _IOW(TPUV1_IOCTL_BASE, 1, struct tpuv1_tc_csr_access)
#endif
